Abstract
This paper presents a 142-154 GHz third-harmonic extracted Class-F oscillator featuring an FoM of -177.1 at 1-MHz offset. In this work, a magnetically coupled dual-core topology is applied to enhance the third harmonic for Class-F operation, which also effectively boosts the negative conductance of the oscillator. The boosted negative conductance relaxes the startup condition in the Colpitts oscillator and improves its phase noise. This oscillator is fabricated in a 22-nm CMOS FDSOI. At 154.5 GHz, the measured PN is -87.4 dBc/Hz at 1-MHz offset, and -101.8 dBc/Hz at 10 MHz offset.
| Original language | English |
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| Title of host publication | 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) |
| Pages | 12-13 |
| Number of pages | 2 |
| DOIs | |
| Publication status | Published - 17 Jun 2022 |
| Event | 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) - Honolulu, HI, USA Duration: 12 Jun 2022 → 17 Jun 2022 |
Conference
| Conference | 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) |
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| Period | 12/06/22 → 17/06/22 |
Keywords
- Phase noise
- Silicon-on-insulator
- Very large scale integration
- Harmonic analysis
- Topology
- Magnetic circuits