A Double-Balanced N-Phase Passive 3 × Sub-Harmonic Down-Conversion Mixer

Mounika Akula; Ajinkya Kale; Johannes Sturm

doi:10.1109/ISCAS51556.2021.9401137

A Double-Balanced N-Phase Passive 3 × Sub-Harmonic Down-Conversion Mixer

Mounika Akula, Ajinkya Kale, Johannes Sturm

Frontend Integr.Circuits&Systems (FEIC)

Research output: Conference proceeding/Chapter in Book/Report/ › Conference Paper › peer-review

Abstract

In this paper, the design of a new passive 3× sub-harmonic down-conversion mixer is proposed based on the concept of N-path architecture. The proposed mixer employs embedded harmonic rejection technique without the need for harmonic weighting stages. 6-phase non-overlapping clock is utilized to obtain triple harmonic mixing and fundamental rejection of the local oscillator. Passive N-path architecture is utilized to enhance harmonic rejection and improve the linearity of the down-conversion mixer. The proposed mixer is designed in 28-nm CMOS technology and is simulated for RF frequency of 3-8 GHz with an LO signal of 1-2.7 GHz. The proposed mixer has a simulated conversion loss of 3.8 dB, IIP3 of 15 dBm and noise figure of 8 dB with fundamental and harmonic suppression of >38 dB.

Original language	English
Title of host publication	2021 IEEE International Symposium on Circuits and Systems (ISCAS)
Pages	1-5
Number of pages	5
DOIs	https://doi.org/10.1109/ISCAS51556.2021.9401137
Publication status	Published - 28 May 2021
Event	2021 IEEE International Symposium on Circuits and Systems (ISCAS) - Daegu, Korea Duration: 22 May 2021 → 28 May 2021

Conference

Conference	2021 IEEE International Symposium on Circuits and Systems (ISCAS)
Period	22/05/21 → 28/05/21

Keywords

Radio frequency
Noise figure
Linearity
Receivers
Harmonic analysis
Mixers
Clocks

Access to Document

10.1109/ISCAS51556.2021.9401137

https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9401137

Cite this

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title = "A Double-Balanced N-Phase Passive 3 × Sub-Harmonic Down-Conversion Mixer",

abstract = "In this paper, the design of a new passive 3× sub-harmonic down-conversion mixer is proposed based on the concept of N-path architecture. The proposed mixer employs embedded harmonic rejection technique without the need for harmonic weighting stages. 6-phase non-overlapping clock is utilized to obtain triple harmonic mixing and fundamental rejection of the local oscillator. Passive N-path architecture is utilized to enhance harmonic rejection and improve the linearity of the down-conversion mixer. The proposed mixer is designed in 28-nm CMOS technology and is simulated for RF frequency of 3-8 GHz with an LO signal of 1-2.7 GHz. The proposed mixer has a simulated conversion loss of 3.8 dB, IIP3 of 15 dBm and noise figure of 8 dB with fundamental and harmonic suppression of >38 dB.",

keywords = "Radio frequency, Noise figure, Linearity, Receivers, Harmonic analysis, Mixers, Clocks",

author = "Mounika Akula and Ajinkya Kale and Johannes Sturm",

year = "2021",

month = may,

day = "28",

doi = "10.1109/ISCAS51556.2021.9401137",

language = "English",

isbn = "978-1-7281-9201-7",

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note = "2021 IEEE International Symposium on Circuits and Systems (ISCAS) ; Conference date: 22-05-2021 Through 28-05-2021",

}

TY - GEN

T1 - A Double-Balanced N-Phase Passive 3 × Sub-Harmonic Down-Conversion Mixer

AU - Akula, Mounika

AU - Kale, Ajinkya

AU - Sturm, Johannes

PY - 2021/5/28

Y1 - 2021/5/28

N2 - In this paper, the design of a new passive 3× sub-harmonic down-conversion mixer is proposed based on the concept of N-path architecture. The proposed mixer employs embedded harmonic rejection technique without the need for harmonic weighting stages. 6-phase non-overlapping clock is utilized to obtain triple harmonic mixing and fundamental rejection of the local oscillator. Passive N-path architecture is utilized to enhance harmonic rejection and improve the linearity of the down-conversion mixer. The proposed mixer is designed in 28-nm CMOS technology and is simulated for RF frequency of 3-8 GHz with an LO signal of 1-2.7 GHz. The proposed mixer has a simulated conversion loss of 3.8 dB, IIP3 of 15 dBm and noise figure of 8 dB with fundamental and harmonic suppression of >38 dB.

AB - In this paper, the design of a new passive 3× sub-harmonic down-conversion mixer is proposed based on the concept of N-path architecture. The proposed mixer employs embedded harmonic rejection technique without the need for harmonic weighting stages. 6-phase non-overlapping clock is utilized to obtain triple harmonic mixing and fundamental rejection of the local oscillator. Passive N-path architecture is utilized to enhance harmonic rejection and improve the linearity of the down-conversion mixer. The proposed mixer is designed in 28-nm CMOS technology and is simulated for RF frequency of 3-8 GHz with an LO signal of 1-2.7 GHz. The proposed mixer has a simulated conversion loss of 3.8 dB, IIP3 of 15 dBm and noise figure of 8 dB with fundamental and harmonic suppression of >38 dB.

KW - Radio frequency

KW - Noise figure

KW - Linearity

KW - Receivers

KW - Harmonic analysis

KW - Mixers

KW - Clocks

UR - https://ieeexplore.ieee.org/document/9401137/

U2 - 10.1109/ISCAS51556.2021.9401137

DO - 10.1109/ISCAS51556.2021.9401137

M3 - Conference Paper

SN - 978-1-7281-9201-7

SP - 1

EP - 5

BT - 2021 IEEE International Symposium on Circuits and Systems (ISCAS)

T2 - 2021 IEEE International Symposium on Circuits and Systems (ISCAS)

Y2 - 22 May 2021 through 28 May 2021

ER -

A Double-Balanced N-Phase Passive 3 × Sub-Harmonic Down-Conversion Mixer

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Keywords

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