In this paper, the design of a new passive 3× sub-harmonic down-conversion mixer is proposed based on the concept of N-path architecture. The proposed mixer employs embedded harmonic rejection technique without the need for harmonic weighting stages. 6-phase non-overlapping clock is utilized to obtain triple harmonic mixing and fundamental rejection of the local oscillator. Passive N-path architecture is utilized to enhance harmonic rejection and improve the linearity of the down-conversion mixer. The proposed mixer is designed in 28-nm CMOS technology and is simulated for RF frequency of 3-8 GHz with an LO signal of 1-2.7 GHz. The proposed mixer has a simulated conversion loss of 3.8 dB, IIP3 of 15 dBm and noise figure of 8 dB with fundamental and harmonic suppression of >38 dB.
|Titel||2021 IEEE International Symposium on Circuits and Systems (ISCAS)|
|Publikationsstatus||Veröffentlicht - 28 Mai 2021|
|Veranstaltung||2021 IEEE International Symposium on Circuits and Systems (ISCAS) - Daegu, Korea|
Dauer: 22 Mai 2021 → 28 Mai 2021
|Konferenz||2021 IEEE International Symposium on Circuits and Systems (ISCAS)|
|Zeitraum||22/05/21 → 28/05/21|