Improvement of SPICE based ESD Protection Models for I/O Protection Modeling

Modeling ESD protection using the System Efficient ESD Design (SEED) methodology enables optimal protection of an IO using TVS and external components. The success of modeling depends on the accuracy of the models. This work shows improvements to SPICE models used to characterize TVS diodes and IC I/O. The improvement is twofold. The transition phases between snapback and main current flow have been adjusted to achieve realistic waveforms for the rise times from 500 ps to 5 ns in a voltage range from Vt1 to the high current region, and complex curvatures of the IV curve are included. The model is capable of operating in generic SPICE and being tested in ADS and LT-SPICE. The paper explains this in detail to enable the reader to apply this modeling principle.