HED-TIE: A wafer-scale approach for fabricating hybrid electronic devices with trench isolated electrodes

S. Banerjee, D. Bülz, D. Solonenko, D. Reuter, C. Deibel, K. Hiller, D.R.T. Zahn, G. Salvan

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@article{102778cb0a714c45a55445c001a66737,

title = "HED-TIE: A wafer-scale approach for fabricating hybrid electronic devices with trench isolated electrodes",

author = "S. Banerjee and D. B{\"u}lz and D. Solonenko and D. Reuter and C. Deibel and K. Hiller and D.R.T. Zahn and G. Salvan",

year = "2017",

doi = "10.1088/1361-6528/aa6713",

language = "English",

}

TY - JOUR

T1 - HED-TIE: A wafer-scale approach for fabricating hybrid electronic devices with trench isolated electrodes

AU - Banerjee, S.

AU - Bülz, D.

AU - Solonenko, D.

AU - Reuter, D.

AU - Deibel, C.

AU - Hiller, K.

AU - Zahn, D.R.T.

AU - Salvan, G.

PY - 2017

Y1 - 2017

UR - http://www.scopus.com/inward/record.url?eid=2-s2.0-85018478568&partnerID=MN8TOARS

U2 - 10.1088/1361-6528/aa6713

DO - 10.1088/1361-6528/aa6713

M3 - Article

JO - Nanotechnology

JF - Nanotechnology

ER -