Design and Multiphysics Simulation of a PCB-Embedded-Package Enclosing a Gallium Nitride System on Chip Grown on a Novel Substrate

This paper presents an advanced packaging concept, for a monolithic Gallium Nitride (GaN) System-on- Chip (GaN High Electron Mobility Transistor half-bridge with integrated gate drivers) grown on a Qromis Substrate Technology (QST(r)) substrate. Since the entire configuration is beyond the state of the art, its viability is assessed through multiphysics simulations before hardware prototyping. The concept is designed, simulated, and optimized in ANSYS considering the thermal management constraints. The thermal simulation results show that the maximum junction temperature is 78 deg C for an estimated power loss of 25W, which is well below the rated value of 150 deg C of the System-on-Chip. The fluid temperatures at the inlet and outlet are 25 deg C and 44 deg C, while the thermal resistance from the SoC junction to the coldplate is evaluated to be 0.16 K/W.