Residue monitor enabled charge-mode adaptive echo-cancellation for simultaneous bidirectional signaling over on-chip interconnects

The full-duplex data communication over on-chip global interconnects suffers from large amounts of amplitude residue echo, leading to the closure of the vertical eye. This work proposes, a residue monitor enabled adaptive echo-cancellation scheme for full-duplex communication with power efficient charge-mode circuits. The proposed architecture employs charge-domain echo cancellation scheme for separating the outbound signal from the inbound signal by precisely controlling the capacitor bank output, thanks to the availability of residue monitor and high precision MOS switches and capacitors at sub-100 nm technology nodes. The residue monitor in the loop tracks the amount of amplitude residue and then sets the control bits, when the loop is locked. Further, this work proposes power efficient charge-mode circuits based replica generation stage, which does not contribute to additional power consumption like in the conventional echo-cancellation schemes. The proposed scheme is implemented at the architectural level with behavioural modeling in Verilog-AMS and also at the circuit level in 1.2 ​V, 65-nm CMOS Technology. The behavioural simulations shows that the residue monitor loop is getting locked while tracking the control voltage generated by the charge regulator for the target near-zero amplitude residue and accordingly control bits to the capacitor bank are set. Circuit level performance shows the functioning at a bidirectional data rate of 20 Gbps over a 1-mm on-chip global interconnect and the extracted received signal has 149 ​mV differential swing at a power consumption of 9.64 ​mW.