Performance Comparison of BAG and Custom Generated Analog Layout for Single-Tail Dynamic Comparator

The advancements in analog electronic design automation (EDA) tools for layout design are still lagging behind than its counterpart digital EDA tools. Due to which, the analog layout design is still done manually therefore time-consuming and difficult to clear the physical verification checks. Over the recent years, many tools are introduced for the automatic layout generation of analog circuits. This paper presents a study of one such popular layout generator for analog layout design referred as Berkeley Analog Generator (BAG). A step by step workflow of the layout generation in BAG is presented and the performance comparison of the automatic layout generated using BAG and full-custom layout for analog circuits is demonstrated. As a test-case, a typical dynamic comparator is used for comparison. The layout of dynamic comparator is done for the same aspect ratios of transistors and specifications in both environments. The performance validation of layouts is done after parasitic extraction in Cadence Spectre environment using TSMC 28 nm standard CMOS process. A clock signal of 50 MHz for the comparator is considered at a supply voltage of 1.0 V.