Exploiting Parasitics to Design a Flip-chip Integrated Transformer Based Matching Network

Pankaj Venuturupalli; Sina Mortezazadeh Mahani; Sondón Santiago Martin; Franz Kuttner; Johannes Sturm

doi:10.1109/Austrochip53290.2021.9576876

Exploiting Parasitics to Design a Flip-chip Integrated Transformer Based Matching Network

Pankaj Venuturupalli, Sina Mortezazadeh Mahani, Sondón Santiago Martin, Franz Kuttner, Johannes Sturm

Frontend Integr.Circuits&Systems (FEIC)

Research output: Conference proceeding/Chapter in Book/Report/ › Conference Paper › peer-review

Abstract

This paper presents a design procedure that involves incorporating the parasitics into the design of a transformer based Matching Network(MN). In this work, flip-chip based integration is opted to connect the on-chip blocks to the external circuitry. At mm-Wave range, parasitics from the bump, ESD and metal traces play a vital role in altering the desired performance of MN. The inductance and capacitance contributed by the ESD structure and the flip-chip bump are extracted from EM simulations which are embedded into the design. This optimization process requires multiple trails which is addressed by SKILL code based spiral inductor layout generation. The MN designed in 28nm CMOS converts a 50Ω load to 4 + 5.1j for a mm-Wave DAC functioning at 28GHz.

Original language	English
Title of host publication	2021 Austrochip Workshop on Microelectronics (Austrochip)
Pages	33-36
Number of pages	4
DOIs	https://doi.org/10.1109/Austrochip53290.2021.9576876
Publication status	Published - 14 Oct 2021
Event	2021 Austrochip Workshop on Microelectronics (Austrochip) - Linz, Austria Duration: 14 Oct 2021 → 14 Oct 2021

Conference

Conference	2021 Austrochip Workshop on Microelectronics (Austrochip)
Period	14/10/21 → 14/10/21

Keywords

Inductance
Codes
Transmitters
Layout
Transformers
Electrostatic discharges
Capacitance
Transformer based matching network

Access to Document

10.1109/Austrochip53290.2021.9576876

https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9576876

Cite this

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title = "Exploiting Parasitics to Design a Flip-chip Integrated Transformer Based Matching Network",

abstract = "This paper presents a design procedure that involves incorporating the parasitics into the design of a transformer based Matching Network(MN). In this work, flip-chip based integration is opted to connect the on-chip blocks to the external circuitry. At mm-Wave range, parasitics from the bump, ESD and metal traces play a vital role in altering the desired performance of MN. The inductance and capacitance contributed by the ESD structure and the flip-chip bump are extracted from EM simulations which are embedded into the design. This optimization process requires multiple trails which is addressed by SKILL code based spiral inductor layout generation. The MN designed in 28nm CMOS converts a 50Ω load to 4 + 5.1j for a mm-Wave DAC functioning at 28GHz.",

keywords = "Inductance, Codes, Transmitters, Layout, Transformers, Electrostatic discharges, Capacitance, Transformer based matching network",

author = "Pankaj Venuturupalli and Mahani, {Sina Mortezazadeh} and Martin, {Sond{\'o}n Santiago} and Franz Kuttner and Johannes Sturm",

year = "2021",

month = oct,

day = "14",

doi = "10.1109/Austrochip53290.2021.9576876",

language = "English",

isbn = "978-1-6654-3662-5",

pages = "33--36",

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note = "2021 Austrochip Workshop on Microelectronics (Austrochip) ; Conference date: 14-10-2021 Through 14-10-2021",

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T1 - Exploiting Parasitics to Design a Flip-chip Integrated Transformer Based Matching Network

AU - Venuturupalli, Pankaj

AU - Mahani, Sina Mortezazadeh

AU - Martin, Sondón Santiago

AU - Kuttner, Franz

AU - Sturm, Johannes

PY - 2021/10/14

Y1 - 2021/10/14

N2 - This paper presents a design procedure that involves incorporating the parasitics into the design of a transformer based Matching Network(MN). In this work, flip-chip based integration is opted to connect the on-chip blocks to the external circuitry. At mm-Wave range, parasitics from the bump, ESD and metal traces play a vital role in altering the desired performance of MN. The inductance and capacitance contributed by the ESD structure and the flip-chip bump are extracted from EM simulations which are embedded into the design. This optimization process requires multiple trails which is addressed by SKILL code based spiral inductor layout generation. The MN designed in 28nm CMOS converts a 50Ω load to 4 + 5.1j for a mm-Wave DAC functioning at 28GHz.

AB - This paper presents a design procedure that involves incorporating the parasitics into the design of a transformer based Matching Network(MN). In this work, flip-chip based integration is opted to connect the on-chip blocks to the external circuitry. At mm-Wave range, parasitics from the bump, ESD and metal traces play a vital role in altering the desired performance of MN. The inductance and capacitance contributed by the ESD structure and the flip-chip bump are extracted from EM simulations which are embedded into the design. This optimization process requires multiple trails which is addressed by SKILL code based spiral inductor layout generation. The MN designed in 28nm CMOS converts a 50Ω load to 4 + 5.1j for a mm-Wave DAC functioning at 28GHz.

KW - Inductance

KW - Codes

KW - Transmitters

KW - Layout

KW - Transformers

KW - Electrostatic discharges

KW - Capacitance

KW - Transformer based matching network

UR - https://ieeexplore.ieee.org/document/9576876/

U2 - 10.1109/Austrochip53290.2021.9576876

DO - 10.1109/Austrochip53290.2021.9576876

M3 - Conference Paper

SN - 978-1-6654-3662-5

SP - 33

EP - 36

BT - 2021 Austrochip Workshop on Microelectronics (Austrochip)

T2 - 2021 Austrochip Workshop on Microelectronics (Austrochip)

Y2 - 14 October 2021 through 14 October 2021

ER -

Exploiting Parasitics to Design a Flip-chip Integrated Transformer Based Matching Network

Abstract

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Keywords

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