Exploiting Parasitics to Design a Flip-chip Integrated Transformer Based Matching Network

Pankaj Venuturupalli, Sina Mortezazadeh Mahani, Sondón Santiago Martin, Franz Kuttner, Johannes Sturm

Research output: Conference proceeding/Chapter in Book/Report/Conference Paperpeer-review


This paper presents a design procedure that involves incorporating the parasitics into the design of a transformer based Matching Network(MN). In this work, flip-chip based integration is opted to connect the on-chip blocks to the external circuitry. At mm-Wave range, parasitics from the bump, ESD and metal traces play a vital role in altering the desired performance of MN. The inductance and capacitance contributed by the ESD structure and the flip-chip bump are extracted from EM simulations which are embedded into the design. This optimization process requires multiple trails which is addressed by SKILL code based spiral inductor layout generation. The MN designed in 28nm CMOS converts a 50Ω load to 4 + 5.1j for a mm-Wave DAC functioning at 28GHz.
Original languageEnglish
Title of host publication2021 Austrochip Workshop on Microelectronics (Austrochip)
Number of pages4
Publication statusPublished - 14 Oct 2021
Event2021 Austrochip Workshop on Microelectronics (Austrochip) - Linz, Austria
Duration: 14 Oct 202114 Oct 2021


Conference2021 Austrochip Workshop on Microelectronics (Austrochip)


  • Inductance
  • Codes
  • Transmitters
  • Layout
  • Transformers
  • Electrostatic discharges
  • Capacitance
  • Transformer based matching network


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