Abstract
This paper presents a design procedure for implementation of a matching network with spurious tones rejection using on-chip transformer for high speed DAC applications. Such circuits are complex to analyze and design, due to the higher order of the network. The presented design procedure involves matching the impedance at a desired center frequency based on the input impedance equation and with the aid of mathematical computational platform to avoid tedious mathematical derivations. A test case is considered with center frequency of 28GHz and detectable spurious tones at 30GHz and 26GHz to verify the proposed design procedure. The designed network matches a 50Ω load to a complex impedance of 12-j5.3 and simultaneously rejects the spurious tones by imposing notch filter at 30GHz and suppressing the other tone at 26GHz by 9.5dB.
| Original language | English |
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| Title of host publication | 2020 Austrochip Workshop on Microelectronics (Austrochip) |
| Pages | 76-79 |
| Number of pages | 4 |
| DOIs | |
| Publication status | Published - 7 Oct 2020 |
| Event | 2020 Austrochip Workshop on Microelectronics (Austrochip) - Vienna, Austria Duration: 7 Oct 2020 → 7 Oct 2020 |
Conference
| Conference | 2020 Austrochip Workshop on Microelectronics (Austrochip) |
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| Period | 7/10/20 → 7/10/20 |
Keywords
- Impedance
- Conferences
- Microelectronics
- Impedance matching
- Bandwidth
- Mathematical model
- Wireless communication