Abstract
This paper presents an approach for reproducing key characteristics of non-linear, high frequency switching transients using a multilayer perceptron neural network. Training data is generated using variable time-step transient imulations
of a half-bridge switching cell of SPICE transistor models together with constrained yet randomized combinations of DClink voltage, drain currents and lumped loop inductances. Using the example of peak turn-OFF voltage overshoot for SiC and Si power transistors, the multilayer perceptrons show a mean error of less than (0.9±1.3)%. The predictions of the multilayer perceptron are then compared to preliminary measurements made using a SiC half-bridge test-bench where good agreement is observed especially for higher drain currents. With continued development, such a neural network could be used in coarse, fixed-time-step simulations of any “half-bridge-based” circuit to offer typically unavailable high-fidelity information with negligible computation time. For example, a designer could choose a transistor and quickly see the limits on allowable loop inductance to avoid excessive voltage overshoot for their simulated current waveforms, or see an estimate for voltage overshoot if the loop inductances are known
of a half-bridge switching cell of SPICE transistor models together with constrained yet randomized combinations of DClink voltage, drain currents and lumped loop inductances. Using the example of peak turn-OFF voltage overshoot for SiC and Si power transistors, the multilayer perceptrons show a mean error of less than (0.9±1.3)%. The predictions of the multilayer perceptron are then compared to preliminary measurements made using a SiC half-bridge test-bench where good agreement is observed especially for higher drain currents. With continued development, such a neural network could be used in coarse, fixed-time-step simulations of any “half-bridge-based” circuit to offer typically unavailable high-fidelity information with negligible computation time. For example, a designer could choose a transistor and quickly see the limits on allowable loop inductance to avoid excessive voltage overshoot for their simulated current waveforms, or see an estimate for voltage overshoot if the loop inductances are known
Original language | English |
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Title of host publication | 2022 IEEE Design Methodologies Conference (DMC) |
DOIs | |
Publication status | Published - 1 Sept 2022 |