A PLL Frequency Synthesizer In 65 nm CMOS for 60 GHz Sliding-IF Transceiver

Yang Liu; Zhiqun Li; Hao Gao

A PLL Frequency Synthesizer In 65 nm CMOS for 60 GHz Sliding-IF Transceiver

Yang Liu, Zhiqun Li, Hao Gao

Research output: Conference proceeding/Chapter in Book/Report/ › Conference Paper › peer-review

Abstract

This paper presents an integer Phase-Locked Loop chip for 802.15.3c sliding-IF transceiver. The PLL is composed of a voltage-controlled oscillator, a current-mode logic divide-by-2, a programmable frequency divider, a phase /frequency detector, a charge pump, and an on-chip loop filter. The proposed PLL chip is fabricated using a 65 nm CMOS process, and the chip size is 1.27 mm². The locking range of the proposed PLL is 23.328 ~ 25.92 GHz, the measured phase noise is -98.8 dBc/Hz@1 MHz, reference spur is -62.4 dBc. The power consumption of the PLL is 45.6 mW including the output buffer.

Original language	English
Title of host publication	2020 15th European Microwave Integrated Circuits Conference (EuMIC)
Publisher	IEEE Computer Society
Pages	221-224
Number of pages	4
ISBN (Print)	978-1-7281-7040-4
Publication status	Published - 15 Jan 2021
Externally published	Yes
Event	2020 15th European Microwave Integrated Circuits Conference (EuMIC) - Utrecht, Netherlands Duration: 10 Jan 2021 → 15 Jan 2021

Conference

Conference	2020 15th European Microwave Integrated Circuits Conference (EuMIC)
Period	10/01/21 → 15/01/21

Keywords

Phase noise
Semiconductor device measurement
Phase measurement
Phase frequency detectors
Frequency conversion
Transceivers
Phase locked loops

Access to Document

https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9337426

Cite this

@inproceedings{98ca2104bbd64971b87db08c64b94011,

title = "A PLL Frequency Synthesizer In 65 nm CMOS for 60 GHz Sliding-IF Transceiver",

abstract = "This paper presents an integer Phase-Locked Loop chip for 802.15.3c sliding-IF transceiver. The PLL is composed of a voltage-controlled oscillator, a current-mode logic divide-by-2, a programmable frequency divider, a phase /frequency detector, a charge pump, and an on-chip loop filter. The proposed PLL chip is fabricated using a 65 nm CMOS process, and the chip size is 1.27 mm2. The locking range of the proposed PLL is 23.328 ~ 25.92 GHz, the measured phase noise is -98.8 dBc/Hz@1 MHz, reference spur is -62.4 dBc. The power consumption of the PLL is 45.6 mW including the output buffer.",

keywords = "Phase noise, Semiconductor device measurement, Phase measurement, Phase frequency detectors, Frequency conversion, Transceivers, Phase locked loops",

author = "Yang Liu and Zhiqun Li and Hao Gao",

year = "2021",

month = jan,

day = "15",

language = "English",

isbn = "978-1-7281-7040-4",

pages = "221--224",

booktitle = "2020 15th European Microwave Integrated Circuits Conference (EuMIC)",

publisher = "IEEE Computer Society",

address = "United States",

note = "2020 15th European Microwave Integrated Circuits Conference (EuMIC) ; Conference date: 10-01-2021 Through 15-01-2021",

}

TY - GEN

T1 - A PLL Frequency Synthesizer In 65 nm CMOS for 60 GHz Sliding-IF Transceiver

AU - Liu, Yang

AU - Li, Zhiqun

AU - Gao, Hao

PY - 2021/1/15

Y1 - 2021/1/15

N2 - This paper presents an integer Phase-Locked Loop chip for 802.15.3c sliding-IF transceiver. The PLL is composed of a voltage-controlled oscillator, a current-mode logic divide-by-2, a programmable frequency divider, a phase /frequency detector, a charge pump, and an on-chip loop filter. The proposed PLL chip is fabricated using a 65 nm CMOS process, and the chip size is 1.27 mm2. The locking range of the proposed PLL is 23.328 ~ 25.92 GHz, the measured phase noise is -98.8 dBc/Hz@1 MHz, reference spur is -62.4 dBc. The power consumption of the PLL is 45.6 mW including the output buffer.

AB - This paper presents an integer Phase-Locked Loop chip for 802.15.3c sliding-IF transceiver. The PLL is composed of a voltage-controlled oscillator, a current-mode logic divide-by-2, a programmable frequency divider, a phase /frequency detector, a charge pump, and an on-chip loop filter. The proposed PLL chip is fabricated using a 65 nm CMOS process, and the chip size is 1.27 mm2. The locking range of the proposed PLL is 23.328 ~ 25.92 GHz, the measured phase noise is -98.8 dBc/Hz@1 MHz, reference spur is -62.4 dBc. The power consumption of the PLL is 45.6 mW including the output buffer.

KW - Phase noise

KW - Semiconductor device measurement

KW - Phase measurement

KW - Phase frequency detectors

KW - Frequency conversion

KW - Transceivers

KW - Phase locked loops

UR - https://ieeexplore.ieee.org/document/9337426/

M3 - Conference Paper

SN - 978-1-7281-7040-4

SP - 221

EP - 224

BT - 2020 15th European Microwave Integrated Circuits Conference (EuMIC)

PB - IEEE Computer Society

T2 - 2020 15th European Microwave Integrated Circuits Conference (EuMIC)

Y2 - 10 January 2021 through 15 January 2021

ER -

A PLL Frequency Synthesizer In 65 nm CMOS for 60 GHz Sliding-IF Transceiver

Abstract

Conference

Keywords

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