Abstract
Wideband beamforming is widely required in the sub-6GHz frequency band for 5G commutation and the next generation wireless communication (B5G). The true time delay is the most crucial component, especially in the sub-6GHz frequency band. This paper presents a new true time delay by using an N-path switch capacitor delay cell to break the tradeoff between bandwidth and delay range by introducing tunable sampling clocks. The non-idealities and limitations are discussed as well. In a 40-nm CMOS technology, the implemented true time delay achieves maximum 900ps delay at 3GHz and 500ps delay at 6GHz with 0.15% variation. Reliability of the design is verified by process variation simulation as well. The proposed topology provides a large delay range with a compact size, which is suitable for sub-6 GHz wideband applications.
Original language | English |
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Title of host publication | 2021 IEEE International Symposium on Circuits and Systems (ISCAS) |
Pages | 1-4 |
Number of pages | 4 |
DOIs | |
Publication status | Published - 28 May 2021 |
Event | 2021 IEEE International Symposium on Circuits and Systems (ISCAS) - Daegu, Korea Duration: 22 May 2021 → 28 May 2021 |
Conference
Conference | 2021 IEEE International Symposium on Circuits and Systems (ISCAS) |
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Period | 22/05/21 → 28/05/21 |
Keywords
- Array signal processing
- Delay effects
- CMOS technology
- Delays
- Topology
- Wideband
- Clocks