Abstract
This paper describes a first prototype of a testbed System on chip (SoC) to design and evaluate different Neuromorphic Deep Neural Networks (NN) cores. The $1.25mm \times 1.25mm$ SoC was fabricated in a 65nm CMOS technology and implements a system composed of an ARM based microprocessor, two memory banks of 32KB, a QSPI serial interface and two NN accelerators. The first one is a novel neuromorphic accelerator consisting of a 5x5 kernel Symmetrical Simplicial (SymSimp) core with a depthwise separable structure, which allows to efficiently implement multi-channel convolutional layers by breaking 3D kernels into 2D kernels. The second is a 3x3 conventional MAC engine to implement the fully connected layers. Experimental results show an energy efficiency of 0.49pJ/OP, which is competitive when compared to similar technology ICs, and extrapolated to the MobileNetworkV2 ImageNet represents a factor of 2 improvement with respect to NVIDIA Jetson Nano.
Original language | English |
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Title of host publication | 2023 IEEE International Symposium on Circuits and Systems (ISCAS) |
DOIs | |
Publication status | Published - 21 Jul 2023 |
Keywords
- VLSI
- Neuromorphic Computing
- Neural Network Accelerators
- CMOS