Piecewise-linear Modelling of CMOS Gates Propagation Delay as a Function of PVT Variations and Aging

Fernando L. Aguirre, Félix Palumbo, Pedro Julián

Research output: Conference proceeding/Chapter in Book/Report/Conference Paperpeer-review

Abstract

Due to the aggressive scaling of transistor dimensions, which took place in the last decades, chip devices are exposed to high electric fields and current densities during normal operation. These working conditions trigger degradation phenomena that compromises the device functionality and rises questions regarding circuit reliability. In this paper we present a simulation based methodology that incorporates the aging phenomena, which might allow to address the reliability aspects during the design phase and pave the way for further life-time projections at the design stage. Piecewise-linear functions are used to model the propagation delays and estimate the correlation between the different degradation mechanisms and the PVT variations.
Original languageEnglish
Title of host publication2021 Argentine Conference on Electronics - Congreso Argentino de Electronica 2021, CAE 2021
PublisherIEEE Computer Society
Pages25-31
Number of pages7
ISBN (Print)9781728175799
DOIs
Publication statusPublished - 12 Mar 2021
Event2021 Argentine Conference on Electronics (CAE) - Bahia Blanca, Argentina
Duration: 11 Mar 202112 Mar 2021

Publication series

Name2021 Argentine Conference on Electronics - Congreso Argentino de Electronica 2021, CAE 2021

Conference

Conference2021 Argentine Conference on Electronics (CAE)
Period11/03/2112/03/21

Keywords

  • Semiconductor device modeling
  • Degradation
  • Logic gates
  • Aging
  • Numerical models
  • Integrated circuit reliability
  • Propagation delay

Fingerprint

Dive into the research topics of 'Piecewise-linear Modelling of CMOS Gates Propagation Delay as a Function of PVT Variations and Aging'. Together they form a unique fingerprint.

Cite this