Abstract
We discuss the architecture, implementation and testing of a neuromorphic Cellular Neural Network (CNN) processor for intelligent IoT devices. The processor is based on a simplicial piecewise linear CNN architecture that allows implementation of linear and nolinear CNNs. A linear array of 64 processing element (PE) with column-shared computation resources, tightly coupled to two data memory caches was synthesized and fabricated in a 55nm CMOS technology using custom layout libraries. The fabricated chip achieves an overall performance of 2.95 TOPS/W with dynamic energy dissipation efficiency of 86.4fJ per OP at V=500mV. The processor can implement different types of processing on 2D data arrays, such as gray-scale morphology, gradient flow, median filters, and approximate Gaussian filters, among others.
Original language | English |
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Title of host publication | 2018 IEEE International Symposium on Circuits and Systems (ISCAS) |
Publisher | IEEE Computer Society |
Pages | 1-4 |
Number of pages | 4 |
ISBN (Print) | 978-1-5386-4882-7 |
DOIs | |
Publication status | Published - 30 May 2018 |
Externally published | Yes |
Event | 2018 IEEE International Symposium on Circuits and Systems (ISCAS) - Florence, Italy Duration: 27 May 2018 → 30 May 2018 |
Conference
Conference | 2018 IEEE International Symposium on Circuits and Systems (ISCAS) |
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Period | 27/05/18 → 30/05/18 |
Keywords
- Arrays
- Neuromorphics
- Registers
- Clocks
- Cellular neural networks
- Parallel processing