Mismatch Analysis of DTCs With an Improved BIST-TDC in 28-nm CMOS

Peng Chen, Jun Yin, Feifei Zhang, Pui-In Mak, Rui P. Martins, Robert Bogdan Staszewski

Research output: Contribution to journalArticlepeer-review


Nonlinearity of a digital-to-time converter (DTC) is pivotal to spur performance in DTC-based all-digital phase-locked-loops (ADPLL). In this paper, we characterize and analyze the mismatch of cascaded-delay-unit DTCs. Through an improved built-in-self-test (BIST) time-to-digital converter (TDC) assisted with phase-to-frequency detector (PFD), a measurement system of sub-half-ps accuracy is constructed to conduct the characterization. Fabricated in 28-nm CMOS, the DTC transfer functions are measured, and mismatches are compared against Monte-Carlo simulation results. The integral nonlinearity (INL) results are compared against each other and converted to the in-band fractional spur level when the DTC would be deployed in the ADPLL. The BIST-TDC system thus characterizes the on-chip delays without expensive equipment or complex setup. The effectiveness of adding a PFD into the ΔΣ loop is validated. The entire BIST system consumes 0.6mW with a system self-calibration algorithm to tackle the analog blocks' nonlinearities.
Original languageEnglish
Article number9524358
Pages (from-to)1-11
Number of pages11
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Issue number99
Publication statusPublished - 2021


  • Delays
  • Clocks
  • Logic gates
  • Monte Carlo methods
  • Loading
  • Capacitance
  • Phase frequency detectors


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