Memory based computation core for nonlinear neural operations

Martin Villemur; Gaspar Tognetti; Pedro Julian

doi:10.1109/CAE.2019.8709266

Memory based computation core for nonlinear neural operations

Martin Villemur, Gaspar Tognetti, Pedro Julian

Research output: Conference proceeding/Chapter in Book/Report/ › Conference Paper › peer-review

Abstract

In this paper we introduce a memory based processor that can produce linear and nonlinear operations. We fabricated an array of 9 cores occupying 1.5mm × 1.5mm in a 130nm technology. Every core has 32 8-bit inputs. The integrated circuit (IC) runs at 85MHz with a power supply of 1.1V and consumes 2.1mW. At this operating point, the IC produces 100 8-bit MOPS and exhibits an efficiency of 21.9 pJ/OP.

Original language	English
Title of host publication	2019 Argentine Conference on Electronics (CAE)
Publisher	IEEE Computer Society
Pages	98-102
Number of pages	5
ISBN (Print)	978-1-7281-1405-7
DOIs	https://doi.org/10.1109/CAE.2019.8709266
Publication status	Published - 15 Mar 2019
Externally published	Yes
Event	2019 Argentine Conference on Electronics (CAE) - Mar del Plata, Argentina Duration: 14 Mar 2019 → 15 Mar 2019

Conference

Conference	2019 Argentine Conference on Electronics (CAE)
Period	14/03/19 → 15/03/19

Keywords

Integrated circuits
Computer architecture
Random access memory
Conferences
Layout
Neurons
Generators

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10.1109/CAE.2019.8709266

https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8709266

Cite this

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title = "Memory based computation core for nonlinear neural operations",

abstract = "In this paper we introduce a memory based processor that can produce linear and nonlinear operations. We fabricated an array of 9 cores occupying 1.5mm × 1.5mm in a 130nm technology. Every core has 32 8-bit inputs. The integrated circuit (IC) runs at 85MHz with a power supply of 1.1V and consumes 2.1mW. At this operating point, the IC produces 100 8-bit MOPS and exhibits an efficiency of 21.9 pJ/OP.",

keywords = "Integrated circuits, Computer architecture, Random access memory, Conferences, Layout, Neurons, Generators",

author = "Martin Villemur and Gaspar Tognetti and Pedro Julian",

year = "2019",

month = mar,

day = "15",

doi = "10.1109/CAE.2019.8709266",

language = "English",

isbn = "978-1-7281-1405-7",

pages = "98--102",

booktitle = "2019 Argentine Conference on Electronics (CAE)",

publisher = "IEEE Computer Society",

address = "United States",

note = "2019 Argentine Conference on Electronics (CAE) ; Conference date: 14-03-2019 Through 15-03-2019",

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TY - GEN

T1 - Memory based computation core for nonlinear neural operations

AU - Villemur, Martin

AU - Tognetti, Gaspar

AU - Julian, Pedro

PY - 2019/3/15

Y1 - 2019/3/15

N2 - In this paper we introduce a memory based processor that can produce linear and nonlinear operations. We fabricated an array of 9 cores occupying 1.5mm × 1.5mm in a 130nm technology. Every core has 32 8-bit inputs. The integrated circuit (IC) runs at 85MHz with a power supply of 1.1V and consumes 2.1mW. At this operating point, the IC produces 100 8-bit MOPS and exhibits an efficiency of 21.9 pJ/OP.

AB - In this paper we introduce a memory based processor that can produce linear and nonlinear operations. We fabricated an array of 9 cores occupying 1.5mm × 1.5mm in a 130nm technology. Every core has 32 8-bit inputs. The integrated circuit (IC) runs at 85MHz with a power supply of 1.1V and consumes 2.1mW. At this operating point, the IC produces 100 8-bit MOPS and exhibits an efficiency of 21.9 pJ/OP.

KW - Integrated circuits

KW - Computer architecture

KW - Random access memory

KW - Conferences

KW - Layout

KW - Neurons

KW - Generators

UR - https://ieeexplore.ieee.org/document/8709266/

U2 - 10.1109/CAE.2019.8709266

DO - 10.1109/CAE.2019.8709266

M3 - Conference Paper

SN - 978-1-7281-1405-7

SP - 98

EP - 102

BT - 2019 Argentine Conference on Electronics (CAE)

PB - IEEE Computer Society

T2 - 2019 Argentine Conference on Electronics (CAE)

Y2 - 14 March 2019 through 15 March 2019

ER -

Memory based computation core for nonlinear neural operations

Abstract

Conference

Keywords

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Cite this