Memory based computation core for nonlinear neural operations

Martin Villemur, Gaspar Tognetti, Pedro Julian

Research output: Conference proceeding/Chapter in Book/Report/Conference Paperpeer-review


In this paper we introduce a memory based processor that can produce linear and nonlinear operations. We fabricated an array of 9 cores occupying 1.5mm × 1.5mm in a 130nm technology. Every core has 32 8-bit inputs. The integrated circuit (IC) runs at 85MHz with a power supply of 1.1V and consumes 2.1mW. At this operating point, the IC produces 100 8-bit MOPS and exhibits an efficiency of 21.9 pJ/OP.
Original languageEnglish
Title of host publication2019 Argentine Conference on Electronics (CAE)
PublisherIEEE Computer Society
Number of pages5
ISBN (Print)978-1-7281-1405-7
Publication statusPublished - 15 Mar 2019
Externally publishedYes
Event2019 Argentine Conference on Electronics (CAE) - Mar del Plata, Argentina
Duration: 14 Mar 201915 Mar 2019


Conference2019 Argentine Conference on Electronics (CAE)


  • Integrated circuits
  • Computer architecture
  • Random access memory
  • Conferences
  • Layout
  • Neurons
  • Generators


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