Design and Experimental Verification of a Single-Phase PFC Stage Based on HERIC Topology

This thesis presents and compares two concepts that serve as power factor correction (PFC) stage: the HERIC and the totem-pole (TP) topology. The most recent bidirectional gallium nitride (GaN) power semiconductor, known as monolithic bidirectional switch (M-BDS), is employed in the HERIC converter. This device enables a decoupling of the AC and DC side of the converter while energizing the boost-inductor. This separation results in improved performance in terms of conducted common mode (CM) emissions towards the grid. The TP topology is a commonly used and widely accepted concept in industry. It is inherently included in the HERIC structure, making a comparison using the same prototype possible.

After a brief overview of the current state of PFC stages, the working principles of the converters are explained and models of their electromagnetic interference (EMI) behavior are derived. A simulation environment is set up to analyze and compare the CM EMI performance and show the superior behavior of the HERIC topology. A fully GaN based prototype with a nominal output power of 1 kW is designed and tested. Special attention is paid to the symmetry of the converter, passive components, and filter structure to fully exploit the advantages of the topology. The obtained HERIC converter highlights a peak efficiency of 98,4% and an efficiency of 97,7% at full load. This is slightly lower than the efficiency of 98,4% at full load of the TP converter, but advancements of the M-BDS technology promise improved efficiency in the near future. EMI improvements of up to 20 dB compared to the TP-PFC stage are gained under the same operating conditions. In particular, the HERIC topology produces significantly lower noise at frequencies above 1 MHz.