A VLSI convolutional neural network architecture for vanishing point computation

M. Villemur; M. Di Federico; P. Julián

doi:10.1109/EAMTA.2015.7237379

A VLSI convolutional neural network architecture for vanishing point computation

M. Villemur, M. Di Federico, P. Julián

Research output: Conference proceeding/Chapter in Book/Report/ › Conference Paper › peer-review

Abstract

This paper presents a VLSI Convolutional Neural Network with special features to implement the Vanishing Point algorithm. The architecture is based on a multi-scale array, with one column processor that implements a neural network with local connectivity, a row processor of SIMD elements that can implement generic convolution and a voting mechanism, which is used by the Vanishing Point algorithm. In addition, a 32-bit 7 pipeline-stage has been designed to sequence all the operations. Simulations of the architecture described in a Hardware description language are shown.

Original language	English
Title of host publication	2015 Argentine School of Micro-Nanoelectronics, Technology and Applications (EAMTA)
Publisher	IEEE Computer Society
Pages	53-57
Number of pages	5
ISBN (Print)	978-1-4799-8017-8
DOIs	https://doi.org/10.1109/EAMTA.2015.7237379
Publication status	Published - 31 Jul 2015
Externally published	Yes
Event	2015 Argentine School of Micro-Nanoelectronics, Technology and Applications (EAMTA) - Villa Maria, Argentina Duration: 30 Jul 2015 → 31 Jul 2015

Conference

Conference	2015 Argentine School of Micro-Nanoelectronics, Technology and Applications (EAMTA)
Period	30/07/15 → 31/07/15

Keywords

Registers
Arrays
Clocks
Convolution
Kernel
Neural networks

Access to Document

10.1109/EAMTA.2015.7237379

https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7237379

Cite this

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title = "A VLSI convolutional neural network architecture for vanishing point computation",

abstract = "This paper presents a VLSI Convolutional Neural Network with special features to implement the Vanishing Point algorithm. The architecture is based on a multi-scale array, with one column processor that implements a neural network with local connectivity, a row processor of SIMD elements that can implement generic convolution and a voting mechanism, which is used by the Vanishing Point algorithm. In addition, a 32-bit 7 pipeline-stage has been designed to sequence all the operations. Simulations of the architecture described in a Hardware description language are shown.",

keywords = "Registers, Arrays, Clocks, Convolution, Kernel, Neural networks",

author = "M. Villemur and Federico, {M. Di} and P. Juli{\'a}n",

year = "2015",

month = jul,

day = "31",

doi = "10.1109/EAMTA.2015.7237379",

language = "English",

isbn = "978-1-4799-8017-8",

pages = "53--57",

booktitle = "2015 Argentine School of Micro-Nanoelectronics, Technology and Applications (EAMTA)",

publisher = "IEEE Computer Society",

address = "United States",

note = "2015 Argentine School of Micro-Nanoelectronics, Technology and Applications (EAMTA) ; Conference date: 30-07-2015 Through 31-07-2015",

}

Villemur, M, Federico, MD & Julián, P 2015, A VLSI convolutional neural network architecture for vanishing point computation. in 2015 Argentine School of Micro-Nanoelectronics, Technology and Applications (EAMTA)., 7237379, IEEE Computer Society, pp. 53-57, 2015 Argentine School of Micro-Nanoelectronics, Technology and Applications (EAMTA), 30/07/15. https://doi.org/10.1109/EAMTA.2015.7237379

TY - GEN

T1 - A VLSI convolutional neural network architecture for vanishing point computation

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AU - Federico, M. Di

AU - Julián, P.

PY - 2015/7/31

Y1 - 2015/7/31

N2 - This paper presents a VLSI Convolutional Neural Network with special features to implement the Vanishing Point algorithm. The architecture is based on a multi-scale array, with one column processor that implements a neural network with local connectivity, a row processor of SIMD elements that can implement generic convolution and a voting mechanism, which is used by the Vanishing Point algorithm. In addition, a 32-bit 7 pipeline-stage has been designed to sequence all the operations. Simulations of the architecture described in a Hardware description language are shown.

AB - This paper presents a VLSI Convolutional Neural Network with special features to implement the Vanishing Point algorithm. The architecture is based on a multi-scale array, with one column processor that implements a neural network with local connectivity, a row processor of SIMD elements that can implement generic convolution and a voting mechanism, which is used by the Vanishing Point algorithm. In addition, a 32-bit 7 pipeline-stage has been designed to sequence all the operations. Simulations of the architecture described in a Hardware description language are shown.

KW - Registers

KW - Arrays

KW - Clocks

KW - Convolution

KW - Kernel

KW - Neural networks

UR - https://ieeexplore.ieee.org/document/7237379/

U2 - 10.1109/EAMTA.2015.7237379

DO - 10.1109/EAMTA.2015.7237379

M3 - Conference Paper

SN - 978-1-4799-8017-8

SP - 53

EP - 57

BT - 2015 Argentine School of Micro-Nanoelectronics, Technology and Applications (EAMTA)

PB - IEEE Computer Society

T2 - 2015 Argentine School of Micro-Nanoelectronics, Technology and Applications (EAMTA)

Y2 - 30 July 2015 through 31 July 2015

ER -

A VLSI convolutional neural network architecture for vanishing point computation

Abstract

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Keywords

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