Abstract
A passive down-conversion mixer in a 65nm buck CMOS process has been presented. The proposed mixer is consisted of a mixer-core and a folded OTA buffer. The mixer has a 3-dB bandwidth of 57~66 GHz, with a conversion gain of -2.7 ~ -5.4 dB. It requires a LO level of -5 dBm. The isolation between LO and RF ports is 10 dB. The total power consumption of the mixer is 1.4 mW, and the chip area is 0.4 mm2.
Original language | English |
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Title of host publication | 2021 IEEE MTT-S International Wireless Symposium (IWS) |
Pages | 1-3 |
Number of pages | 3 |
DOIs | |
Publication status | Published - 26 May 2021 |
Event | 2021 IEEE MTT-S International Wireless Symposium (IWS) - Nanjing, China Duration: 23 May 2021 → 26 May 2021 |
Conference
Conference | 2021 IEEE MTT-S International Wireless Symposium (IWS) |
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Period | 23/05/21 → 26/05/21 |
Keywords
- Radio frequency
- Wireless communication
- Power demand
- Bandwidth
- Receivers
- CMOS process
- Mixers