A 14b 2GS/s DAC with >87 dB SFDR in 0.18 μm BiCMOS Technology

Hongfei Hu; Qian Qi; Jian Xiao; Yufeng Guo; Hao Gao; Yi Zhang

doi:10.1109/ICMMT52847.2021.9618087

A 14b 2GS/s DAC with >87 dB SFDR in 0.18 μm BiCMOS Technology

Hongfei Hu, Qian Qi, Jian Xiao, Yufeng Guo, Hao Gao, Yi Zhang

Millimeter Wave Technologies (mmW)

Research output: Conference proceeding/Chapter in Book/Report/ › Conference Paper › peer-review

Abstract

This paper presents a 14b 2GS/s DAC in 0.18 μm BiCMOS. In order to improve the linearity and dynamic performance of the DAC, SiGe HBTs are adopted in this scheme as the DAC current sources, while the digital circuit is fabricated in CMOS technology for the purpose of reducing power consumption and saving chip area. A R-2R resistor ladder, a two-stage segmented decoding circuit and a special current cell is designed in this paper to overcome shortcomings of SiGe HBT in the DAC. The post simulation results show that the DAC achieves a SFDR of 87dB at Nyquist-rate.

Original language	English
Title of host publication	2021 International Conference on Microwave and Millimeter Wave Technology (ICMMT)
Pages	1-3
Number of pages	3
DOIs	https://doi.org/10.1109/ICMMT52847.2021.9618087
Publication status	Published - 26 May 2021
Event	2021 International Conference on Microwave and Millimeter Wave Technology (ICMMT) - Nanjing, China Duration: 23 May 2021 → 26 May 2021

Conference

Conference	2021 International Conference on Microwave and Millimeter Wave Technology (ICMMT)
Period	23/05/21 → 26/05/21

Keywords

Semiconductor device modeling
Resistors
Power demand
Simulation
Millimeter wave technology
CMOS technology
BiCMOS integrated circuits

Access to Document

10.1109/ICMMT52847.2021.9618087

https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9618087

Cite this

@inproceedings{101db5e435b3488dbb60b63ff2706e2a,

title = "A 14b 2GS/s DAC with >87 dB SFDR in 0.18 μm BiCMOS Technology",

abstract = "This paper presents a 14b 2GS/s DAC in 0.18 μm BiCMOS. In order to improve the linearity and dynamic performance of the DAC, SiGe HBTs are adopted in this scheme as the DAC current sources, while the digital circuit is fabricated in CMOS technology for the purpose of reducing power consumption and saving chip area. A R-2R resistor ladder, a two-stage segmented decoding circuit and a special current cell is designed in this paper to overcome shortcomings of SiGe HBT in the DAC. The post simulation results show that the DAC achieves a SFDR of 87dB at Nyquist-rate.",

keywords = "Semiconductor device modeling, Resistors, Power demand, Simulation, Millimeter wave technology, CMOS technology, BiCMOS integrated circuits",

author = "Hongfei Hu and Qian Qi and Jian Xiao and Yufeng Guo and Hao Gao and Yi Zhang",

year = "2021",

month = may,

day = "26",

doi = "10.1109/ICMMT52847.2021.9618087",

language = "English",

isbn = "978-1-6654-3438-6",

pages = "1--3",

booktitle = "2021 International Conference on Microwave and Millimeter Wave Technology (ICMMT)",

note = "2021 International Conference on Microwave and Millimeter Wave Technology (ICMMT) ; Conference date: 23-05-2021 Through 26-05-2021",

}

TY - GEN

T1 - A 14b 2GS/s DAC with >87 dB SFDR in 0.18 μm BiCMOS Technology

AU - Hu, Hongfei

AU - Qi, Qian

AU - Xiao, Jian

AU - Guo, Yufeng

AU - Gao, Hao

AU - Zhang, Yi

PY - 2021/5/26

Y1 - 2021/5/26

N2 - This paper presents a 14b 2GS/s DAC in 0.18 μm BiCMOS. In order to improve the linearity and dynamic performance of the DAC, SiGe HBTs are adopted in this scheme as the DAC current sources, while the digital circuit is fabricated in CMOS technology for the purpose of reducing power consumption and saving chip area. A R-2R resistor ladder, a two-stage segmented decoding circuit and a special current cell is designed in this paper to overcome shortcomings of SiGe HBT in the DAC. The post simulation results show that the DAC achieves a SFDR of 87dB at Nyquist-rate.

AB - This paper presents a 14b 2GS/s DAC in 0.18 μm BiCMOS. In order to improve the linearity and dynamic performance of the DAC, SiGe HBTs are adopted in this scheme as the DAC current sources, while the digital circuit is fabricated in CMOS technology for the purpose of reducing power consumption and saving chip area. A R-2R resistor ladder, a two-stage segmented decoding circuit and a special current cell is designed in this paper to overcome shortcomings of SiGe HBT in the DAC. The post simulation results show that the DAC achieves a SFDR of 87dB at Nyquist-rate.

KW - Semiconductor device modeling

KW - Resistors

KW - Power demand

KW - Simulation

KW - Millimeter wave technology

KW - CMOS technology

KW - BiCMOS integrated circuits

UR - https://ieeexplore.ieee.org/document/9618087/

U2 - 10.1109/ICMMT52847.2021.9618087

DO - 10.1109/ICMMT52847.2021.9618087

M3 - Conference Paper

SN - 978-1-6654-3438-6

SP - 1

EP - 3

BT - 2021 International Conference on Microwave and Millimeter Wave Technology (ICMMT)

T2 - 2021 International Conference on Microwave and Millimeter Wave Technology (ICMMT)

Y2 - 23 May 2021 through 26 May 2021

ER -

A 14b 2GS/s DAC with >87 dB SFDR in 0.18 μm BiCMOS Technology

Abstract

Conference

Keywords

Access to Document

Other files and links

Fingerprint

Cite this