Abstract
Nonlinearity of a digital-to-time converter (DTC) is pivotal to spur performance in DTC-based all-digital phase-locked-loops (ADPLL). In this paper, we characterize and analyze the mismatch of cascaded-delay-unit DTCs. Through an improved built-in-self-test (BIST) time-to-digital converter (TDC) assisted with phase-to-frequency detector (PFD), a measurement system of sub-half-ps accuracy is constructed to conduct the characterization. Fabricated in 28-nm CMOS, the DTC transfer functions are measured, and mismatches are compared against Monte-Carlo simulation results. The integral nonlinearity (INL) results are compared against each other and converted to the in-band fractional spur level when the DTC would be deployed in the ADPLL. The BIST-TDC system thus characterizes the on-chip delays without expensive equipment or complex setup. The effectiveness of adding a PFD into the ΔΣ loop is validated. The entire BIST system consumes 0.6mW with a system self-calibration algorithm to tackle the analog blocks' nonlinearities.
Originalsprache | Englisch |
---|---|
Aufsatznummer | 9524358 |
Seiten (von - bis) | 1-11 |
Seitenumfang | 11 |
Fachzeitschrift | IEEE Transactions on Circuits and Systems I: Regular Papers |
Jahrgang | PP |
Ausgabenummer | 99 |
DOIs | |
Publikationsstatus | Veröffentlicht - 2021 |