This thesis addresses the design flow for SPAD devices in CMOS technology. The proposed methodology consists of developing VERILOG-A SPAD models for electrical simulation that are required to accurately design in-pixel quenching circuitry. This has been achieved by combing analytical models with data fitting based on TCAD simulations of physical SPAD structures. On the one hand, VERILOF-A is the best framework to develop complex analog mixed-signal models that can be co-simulated in CADENCE SPECTRE or SYNOPSYS HSPICE with analog and digital, transistor level or behavioral electronics modules. On the other hand, the SPAD behavior relies on complex semiconductor physics that is accurately modeled by TCAS tools such as Silvaco. However, these tools are used to describe static phenomena. Data fitting is used to bridge the gap between these two design platforms.